1. Field of the Invention
The invention relates to the process for providing oxidation enhancement dopants into a semiconductor substrate using Gas Immersion Laser Doping ("GILD"), particularly for forming an oxide layer.
2. Description of the Related Art
A prevalent trend in the semiconductor industry is to increase the density of semiconductor devices formed on silicon substrates.
Programmable logic devices (PLD) are circuits which can be configured by a user to perform logic functions or serve as memory arrays. Generally, PLDs include a programmable array of cells and array control circuitry which is utilized to program the array with the desired implementation. The programmable array comprises a series of low-voltage, short channel floating gate transistors which store charge to reflect whether a particular cell is programmed with a bit of data. The programmed array reflects a particular user's individual configuration for the programmable device, allowing users to customize the programmable logic device for a number of different applications.
One type of programmable logic device which has become popular due to its performance and cost characteristics are electrically erasable complementary metal oxide semiconductor (E.sup.2 CMOS) PLDs.
E.sup.2 CMOS technology is based on the concept of a stored charge on a floating gate. Electrons are transferred to the gate through a physical mechanism known as Fowler-Nordheim tunneling. For an electrically erasable cell, a tunnel oxide is present between the source and drain regions and the floating gate that is about one-third of the thickness of a traditional transistor gate oxide. Fowler-Nordheim tunneling involves placing a potential across the tunnel oxide which distorts the electric field and allows electrons to traverse the tunnel oxide upon which they become trapped on a floating gate.
The control circuitry of the cell--the program transistors or so-called write transistors--essentially comprise high voltage transistors capable of sustaining high electric fields. So called read transistors, which operate at low voltage, include a first junction, second junction and gate (defined by the word line of the device). The control gate includes the program junction which is separated from the floating gate by an oxide layer having a thickness of approximately 180 .ANG.. The program transistor includes a first junction, second junction and a gate which also rests on the oxide layer. The memory cell will also include a floating gate, separated from the program junction by a tunnel oxide which may be activated by the control gate. The thickness of tunnel oxide is in a range of approximately 80-100 .ANG..
When programming or erasing the device, a voltage is applied between the program and control gate nodes. The direction of the voltage determines whether the cell is erased or programmed. When erasing, the control gate is given a positive voltage and the program node is grounded. When programming, the program node voltage is elevated and the control gate is grounded.
Several alternative designs of memory cells are utilized. Characteristically, in an E.sup.2 CMOS PLD, four types of transistors are required: high voltage P channel, high voltage N channel, low voltage P channel, and low voltage N channel.
The trend of E.sup.2 CMOS PLD devices has been toward lower and lower supply voltages. Consequently, this has required a corresponding scaling down of the oxide layers in the various transistors and at the program junctions. As the oxide thicknesses have been reduced, it is particularly important that the program junction oxide is uniform and of high quality in order to ensure reliable electrical characteristics.
U.S. Patent Applications entitled AN INTEGRATED CIRCUIT HAVING, AND PROCESS PROVIDING, DIFFERENT OXIDE LAYER THICKNESSES ON A SUBSTRATE and MULTIPLE GATE OXIDE THICKNESSES ON A WAFER SUBSTRATE referenced above discloses methods for forming different oxide thicknesses on a semiconductor substrate. In particular, these applications disclose a method for forming a write transistor with a first oxide thickness, a read transistor with a second oxide thickness and a tunnel oxide with a third oxide thickness.
In formation of oxides in general, it is generally known that the provision of phosphorus or arsenic into the silicon substrate prior to forming the oxide by thermal formation in an oxygen atmosphere results in a different growth of oxide between the region overlying the phosphorus or arsenic deposited region and the region of the substrate where no phosphorus or arsenic has been deposited. However, where the oxide thicknesses are relatively small, care must be taken not to damage the surface of the silicon substrate, as growth of the oxide will be impaired.
Conventionally, phosphorus or arsenic may be beam-line ion implanted at a relatively low energy into the substrate. However, ion implantation can cause substrate damage which is difficult to anneal out using conventional methods, and compromise the quality or uniformity of the oxide grown for small thicknesses. Thus, semiconductor device yield and reliability is reduced leading to higher manufacturing costs.
Therefore, it is desirable to have a method for forming reliable high quality and uniform oxide at reduced manufacturing costs. In particular, it is desirable to have a method to form a uniform relatively small thickness oxide layer over a program junction. Further, it is desirable to provide an E.sup.2 PROM memory cell having a uniform relatively small thickness oxide layer over a program junction in order to ensure reliable memory cell operation.